The present invention concerns the production of multiple logic signals with arbitrary yet highly accurate timing relative to a machine cycle.
A sequential digital state machine typically uses a machine cycle to cause logical signals to occur at known times The machine cycle is also called a system clock signal. If only one system clock signal phase is available, then the finest timing resolution that can be attained is one clock period. Finer resolutions can be obtained by producing copies of the system clock signal which are offset in phase. If multi-phases are produced as sub-multiples of the period of the system clock signal, then the improved timing resolution is the period of the sub-multiple. For example, if a system clock signal is divided into two phases, then the improved timing resolution is one half the period of the system clock signal.
For some applications within very large scale integrate (VLSI) circuits maximum system performance requires arbitrarily fine resolution of timing for a finite set of signals. The resolution of timing may be so fine that the production of such signals using sub-multiple phases of the system clock signal would require more sub-multiple phases than are generally feasible. One alternative to creating sub-multiple phases of the system clock signal is to generate copies of the system clock signal with just the phases which are required by any set of logic signals.